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[tests] add cover demo #926
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[t1emu] add coverage for different sew / vmul / vl [t1emu] add coverage for different overlap type with lsu
Signed-off-by: Clo91eaf <[email protected]>
Signed-off-by: Clo91eaf <[email protected]>
Signed-off-by: Clo91eaf <[email protected]>
Please add a documentation about how to add coverage points, tests. |
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Signed-off-by: Clo91eaf <[email protected]>
Signed-off-by: Clo91eaf <[email protected]>
"name": "vmv_v_i", | ||
"description": "single instruction vmv.v.i" |
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How do you align the RTL coverpoint(from LTL) to this name?
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There are actually two rules here:
- When Chisel lowers to sv, it will replace
.
in the label of LTL in the Chisel code with_
. - VCS enables the assertions based on wildcard matching of the name in the full design:
If a full hierarchical name is provided, such as A.C, vcs will determine the matching label. If only the last name is provided, such as C, vcs will still match the same label A.C. It is worth noting that if If there is another name, such as B.C, then vcs will match both A.C and B.C. And Some wildcard operation are also allowed, refer tothe Coverage Technology Reference Manual of VCS
So the 'vmv_v_i' here actually corresponds to the full hierachy name 'TestBench.dut.verification.vmv_v_i'
#837
Add coverpoint support to the simplest mlir.hello test case as a cover demo.