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[tests] add cover demo #926

Merged
merged 7 commits into from
Jan 7, 2025
Merged

[tests] add cover demo #926

merged 7 commits into from
Jan 7, 2025

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Clo91eaf
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@Clo91eaf Clo91eaf commented Jan 6, 2025

#837

Add coverpoint support to the simplest mlir.hello test case as a cover demo.

  • Added hello.json file at the same level as the source code to describe coverpoints.
  • Modified default.nix build script to use jq to parse hello.json into URG coverage hierarchy format.

[t1emu] add coverage for different sew / vmul / vl

[t1emu] add coverage for different overlap type with lsu
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Please add a documentation about how to add coverage points, tests.

@Clo91eaf Clo91eaf force-pushed the Clo91eaf/cover-demo branch from 25a28e0 to 53d4202 Compare January 6, 2025 08:24
Comment on lines +351 to +352
"name": "vmv_v_i",
"description": "single instruction vmv.v.i"
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How do you align the RTL coverpoint(from LTL) to this name?

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@Clo91eaf Clo91eaf Jan 7, 2025

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There are actually two rules here:

  1. When Chisel lowers to sv, it will replace . in the label of LTL in the Chisel code with _.
  2. VCS enables the assertions based on wildcard matching of the name in the full design:
    If a full hierarchical name is provided, such as A.C, vcs will determine the matching label. If only the last name is provided, such as C, vcs will still match the same label A.C. It is worth noting that if If there is another name, such as B.C, then vcs will match both A.C and B.C. And Some wildcard operation are also allowed, refer to the Coverage Technology Reference Manual of VCS
    So the 'vmv_v_i' here actually corresponds to the full hierachy name 'TestBench.dut.verification.vmv_v_i'

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@sequencer sequencer merged commit 6556a44 into master Jan 7, 2025
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@sequencer sequencer deleted the Clo91eaf/cover-demo branch January 7, 2025 11:01
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2 participants