colorlight_5a_75x: Disable full_memory_we for l2 cache by default

Leads to an increase in DP16KD, first noticed in
enjoy-digital/liteeth#70.
With full_mem_we:
```
Info: 	              DP16KD:    41/   56    73%
```
Without:
```
Info: 	              DP16KD:    29/   56    51%
```

litex_boards/targets/colorlight_5a_75x.py

@@ -152,9 +152,11 @@ def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False,
             else:
                 sdram_cls  = M12L16161A
             self.add_sdram("sdram",
-                phy           = self.sdrphy,
-                module        = sdram_cls(sys_clk_freq, sdram_rate),
-                l2_cache_size = kwargs.get("l2_size", 8192)
+                phy                     = self.sdrphy,
+                module                  = sdram_cls(sys_clk_freq, sdram_rate),
+                l2_cache_size           = kwargs.get("l2_size", 8192),
+                l2_cache_full_memory_we = False,
+
             )
 
         # Ethernet / Etherbone ---------------------------------------------------------------------