Home

Jump to bottom

Greg Kasprowicz edited this page Sep 1, 2022 · 2 revisions

The module was developed at the WUT by Wojciech Rucło as an engineering thesis. We plan to test it with AFCK board. Specification:

dual AD9234-1000 12bit, 1GSs ADC
4x SMA inputs, 50Ohm, max 1W
1x MMCX clock reference input
clock distribution based on AD9528BCPZ
compatible with 1.8 and 2.5V VADJ
it requires LA lane only HPC FMC with 8 Gigabit DP lanes
flexible AFE with -/- 50mV, 500mV and 5V range
independent offset regulation +/- 5V
1x MMCXLVTTL trigger input/output
monitoring of all power rails
max power consumption: 21.5W

top view

bottom view