reduce FPGA frequency to 15MHz to accomodate FPU

esl-epfl · Oct 16, 2023 · 1a01423 · 1a01423
1 parent a1a938b
commit 1a01423
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl b/hw/fpga/scripts/xilinx_generate_clk_wizard.tcl
@@ -5,7 +5,7 @@
 
 set design_name      xilinx_clk_wizard
 set in_clk_freq_MHz  125
-set out_clk_freq_MHz 20
+set out_clk_freq_MHz 15
 
 # Select board
 set_property -name "board_part_repo_paths" -value "[file normalize "../../../hw/fpga/board_files/"]" -objects [current_project]
@@ -25,7 +25,7 @@ set_property -dict [ list \
  CONFIG.CLKIN1_JITTER_PS {80.0} \
  CONFIG.CLKOUT1_JITTER {172.798} \
  CONFIG.CLKOUT1_PHASE_ERROR {96.948} \
- CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20} \
+ CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {15} \
  CONFIG.MMCM_CLKFBOUT_MULT_F {8.000} \
  CONFIG.MMCM_CLKIN1_PERIOD {8.000} \
  CONFIG.MMCM_CLKOUT0_DIVIDE_F {50.000} \

diff --git a/sw/device/target/pynq-z2/x-heep.h b/sw/device/target/pynq-z2/x-heep.h
@@ -12,7 +12,7 @@ extern "C" {
 #endif  // __cplusplus
 
 
-#define REFERENCE_CLOCK_Hz 20*1000*1000
+#define REFERENCE_CLOCK_Hz 15*1000*1000
 #define UART_BAUDRATE 115200
 #define TARGET_PYNQ_Z2 1