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Added im2col spc HAL & fixes
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@TommiTerza
TommiTerza committed Sep 5, 2024
1 parent 490a402 commit 8884fbf
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60 changes: 60 additions & 0 deletions hw/core-v-mini-mcu/core_v_mini_mcu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -459,6 +459,66 @@ module core_v_mini_mcu
assign memory_subsystem_banks_powergate_iso_n[1] = memory_subsystem_pwr_ctrl_out[1].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[1] = memory_subsystem_pwr_ctrl_out[1].retentive_en_n;
assign memory_subsystem_clkgate_en_n[1] = memory_subsystem_pwr_ctrl_out[1].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[2] = memory_subsystem_pwr_ctrl_out[2].pwrgate_en_n;

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@davideschiavone

davideschiavone Sep 5, 2024

Member

number of banks should be 2 by default
assign memory_subsystem_pwr_ctrl_in[2].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[2];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[2] = memory_subsystem_pwr_ctrl_out[2].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[2] = memory_subsystem_pwr_ctrl_out[2].retentive_en_n;
assign memory_subsystem_clkgate_en_n[2] = memory_subsystem_pwr_ctrl_out[2].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[3] = memory_subsystem_pwr_ctrl_out[3].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[3].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[3];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[3] = memory_subsystem_pwr_ctrl_out[3].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[3] = memory_subsystem_pwr_ctrl_out[3].retentive_en_n;
assign memory_subsystem_clkgate_en_n[3] = memory_subsystem_pwr_ctrl_out[3].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[4] = memory_subsystem_pwr_ctrl_out[4].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[4].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[4];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[4] = memory_subsystem_pwr_ctrl_out[4].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[4] = memory_subsystem_pwr_ctrl_out[4].retentive_en_n;
assign memory_subsystem_clkgate_en_n[4] = memory_subsystem_pwr_ctrl_out[4].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[5] = memory_subsystem_pwr_ctrl_out[5].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[5].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[5];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[5] = memory_subsystem_pwr_ctrl_out[5].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[5] = memory_subsystem_pwr_ctrl_out[5].retentive_en_n;
assign memory_subsystem_clkgate_en_n[5] = memory_subsystem_pwr_ctrl_out[5].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[6] = memory_subsystem_pwr_ctrl_out[6].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[6].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[6];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[6] = memory_subsystem_pwr_ctrl_out[6].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[6] = memory_subsystem_pwr_ctrl_out[6].retentive_en_n;
assign memory_subsystem_clkgate_en_n[6] = memory_subsystem_pwr_ctrl_out[6].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[7] = memory_subsystem_pwr_ctrl_out[7].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[7].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[7];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[7] = memory_subsystem_pwr_ctrl_out[7].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[7] = memory_subsystem_pwr_ctrl_out[7].retentive_en_n;
assign memory_subsystem_clkgate_en_n[7] = memory_subsystem_pwr_ctrl_out[7].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[8] = memory_subsystem_pwr_ctrl_out[8].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[8].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[8];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[8] = memory_subsystem_pwr_ctrl_out[8].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[8] = memory_subsystem_pwr_ctrl_out[8].retentive_en_n;
assign memory_subsystem_clkgate_en_n[8] = memory_subsystem_pwr_ctrl_out[8].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[9] = memory_subsystem_pwr_ctrl_out[9].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[9].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[9];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[9] = memory_subsystem_pwr_ctrl_out[9].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[9] = memory_subsystem_pwr_ctrl_out[9].retentive_en_n;
assign memory_subsystem_clkgate_en_n[9] = memory_subsystem_pwr_ctrl_out[9].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[10] = memory_subsystem_pwr_ctrl_out[10].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[10].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[10];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[10] = memory_subsystem_pwr_ctrl_out[10].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[10] = memory_subsystem_pwr_ctrl_out[10].retentive_en_n;
assign memory_subsystem_clkgate_en_n[10] = memory_subsystem_pwr_ctrl_out[10].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[11] = memory_subsystem_pwr_ctrl_out[11].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[11].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[11];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[11] = memory_subsystem_pwr_ctrl_out[11].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[11] = memory_subsystem_pwr_ctrl_out[11].retentive_en_n;
assign memory_subsystem_clkgate_en_n[11] = memory_subsystem_pwr_ctrl_out[11].clkgate_en_n;

for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
assign external_subsystem_powergate_switch_no[i] = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
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1 change: 1 addition & 0 deletions hw/ip_examples/im2col_spc/im2col_spc.core
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ filesets:
files_rtl:
depend:
- pulp-platform.org::common_cells
- x-heep:ip:dma
files:
- rtl/im2col_spc_reg_pkg.sv
- rtl/im2col_spc_reg_top.sv
Expand Down
51 changes: 17 additions & 34 deletions hw/ip_examples/im2col_spc/rtl/im2col_spc.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,29 +33,12 @@ module im2col_spc
import core_v_mini_mcu_pkg::*;
import dma_if_pkg::*;
import im2col_spc_reg_pkg::*;
import dma_reg_pkg::*;

/*_________________________________________________________________________________________________________________________________ */

/* Parameter definition */

/* DMA register offsets */
localparam DMA_DIMENSIONALITY_OFFSET = 32'h3C;
localparam DMA_SRC_PTR_OFFSET = 32'h0;
localparam DMA_DST_PTR_OFFSET = 32'h4;
localparam DMA_INC_SRC_D1_OFFSET = 32'h18;
localparam DMA_INC_SRC_D2_OFFSET = 32'h1C;
localparam DMA_INC_DST_D1_OFFSET = 32'h20;
localparam DMA_INC_DST_D2_OFFSET = 32'h24;
localparam DMA_SIZE_D2_OFFSET = 32'h10;
localparam DMA_SIZE_D1_OFFSET = 32'hC;
localparam DMA_SRC_DATATYPE_OFFSET = 32'h2C;
localparam DMA_DST_DATATYPE_OFFSET = 32'h30;
localparam DMA_TOP_PAD_OFFSET = 32'h44;
localparam DMA_BOTTOM_PAD_OFFSET = 32'h48;
localparam DMA_RIGHT_PAD_OFFSET = 32'h4C;
localparam DMA_LEFT_PAD_OFFSET = 32'h50;
localparam DMA_SLOTS_OFFSET = 32'h28;

/* FIFO dimension */
localparam FIFO_DEPTH = 8;

Expand Down Expand Up @@ -435,127 +418,127 @@ module im2col_spc
dma_wdata = 32'h1;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_DIMENSIONALITY_OFFSET;
{25'h0, dma_reg_pkg::DMA_DIM_CONFIG_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_SLOTS: begin
dma_wdata = {reg2hw.slot.tx_trigger_slot.q, reg2hw.slot.rx_trigger_slot.q};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_SLOTS_OFFSET;
{25'h0, dma_reg_pkg::DMA_SLOT_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_SRC_DATATYPE: begin
dma_wdata = {30'h0, reg2hw.data_type.q} & 32'h3;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_SRC_DATATYPE_OFFSET;
{25'h0, dma_reg_pkg::DMA_SRC_DATA_TYPE_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_DST_DATATYPE: begin
dma_wdata = {30'h0, reg2hw.data_type.q} & 32'h3;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_DST_DATATYPE_OFFSET;
{25'h0, dma_reg_pkg::DMA_DST_DATA_TYPE_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_TOP_PAD: begin
dma_wdata = {24'h0, fifo_output.n_zeros_top};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_TOP_PAD_OFFSET;
{25'h0, dma_reg_pkg::DMA_PAD_TOP_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_BOTTOM_PAD: begin
dma_wdata = {24'h0, fifo_output.n_zeros_bottom};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_BOTTOM_PAD_OFFSET;
{25'h0, dma_reg_pkg::DMA_PAD_BOTTOM_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_LEFT_PAD: begin
dma_wdata = {24'h0, fifo_output.n_zeros_left};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_LEFT_PAD_OFFSET;
{25'h0, dma_reg_pkg::DMA_PAD_LEFT_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_RIGHT_PAD: begin
dma_wdata = {24'h0, fifo_output.n_zeros_right};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_RIGHT_PAD_OFFSET;
{25'h0, dma_reg_pkg::DMA_PAD_RIGHT_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_INPUT_PTR: begin
dma_wdata = fifo_output.input_ptr;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_SRC_PTR_OFFSET;
{25'h0, dma_reg_pkg::DMA_SRC_PTR_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_OUTPUT_PTR: begin
dma_wdata = fifo_output.output_ptr;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_DST_PTR_OFFSET;
{25'h0, dma_reg_pkg::DMA_DST_PTR_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_INC_SRC_D1: begin
dma_wdata = (1 << {28'h0, reg2hw.log_strides_d1.q}) << (2 - reg2hw.data_type.q) & 32'h3f;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_INC_SRC_D1_OFFSET;
{25'h0, dma_reg_pkg::DMA_SRC_PTR_INC_D1_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_INC_SRC_D2: begin
dma_wdata = {9'h0, fifo_output.in_inc_d2} << (2 - reg2hw.data_type.q) & 32'h7fffff;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_INC_SRC_D2_OFFSET;
{25'h0, dma_reg_pkg::DMA_SRC_PTR_INC_D2_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_INC_DST_D1: begin
dma_wdata = (4 >> reg2hw.data_type.q) & 32'h3f;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_INC_DST_D1_OFFSET;
{25'h0, dma_reg_pkg::DMA_DST_PTR_INC_D1_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_INC_DST_D2: begin
dma_wdata = (4 >> reg2hw.data_type.q) & 32'h7fffff;
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_INC_DST_D2_OFFSET;
{25'h0, dma_reg_pkg::DMA_DST_PTR_INC_D2_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_SIZE_D2: begin
dma_wdata = {16'h0, fifo_output.size_du_d2};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_SIZE_D2_OFFSET;
{25'h0, dma_reg_pkg::DMA_SIZE_D2_OFFSET};
dma_regintfc_start = 1'b1;
end

WRITE_SIZE_D1: begin
dma_wdata = {16'h0, fifo_output.size_du_d1};
dma_addr = core_v_mini_mcu_pkg::DMA_START_ADDRESS +
dma_trans_free_channel * core_v_mini_mcu_pkg::DMA_CH_SIZE +
DMA_SIZE_D1_OFFSET;
{25'h0, dma_reg_pkg::DMA_SIZE_D1_OFFSET};
dma_regintfc_start = 1'b1;
end

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