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Modified AO_SPC parameter
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@TommiTerza
TommiTerza committed Sep 2, 2024
1 parent 1722ea3 commit ca6cb09
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Showing 8 changed files with 93 additions and 38 deletions.
16 changes: 9 additions & 7 deletions hw/core-v-mini-mcu/ao_peripheral_subsystem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,9 @@ module ao_peripheral_subsystem
import reg_pkg::*;
import power_manager_pkg::*;
#(
parameter AO_SPC_NUM = 0,
//do not touch these parameters
parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT
) (
Expand All @@ -17,8 +19,8 @@ module ao_peripheral_subsystem
input reg_req_t slave_req_i,
output reg_rsp_t slave_resp_o,

input reg_req_t spc2ao_req_i [ao_spc_pkg::AO_SPC_NUM-1:0],
output reg_rsp_t ao2spc_resp_o[ao_spc_pkg::AO_SPC_NUM-1:0],
input reg_req_t spc2ao_req_i [AO_SPC_NUM_RND-1:0],
output reg_rsp_t ao2spc_resp_o[AO_SPC_NUM_RND-1:0],

// SOC CTRL
input logic boot_select_i,
Expand Down Expand Up @@ -229,21 +231,21 @@ module ao_peripheral_subsystem

/* SPC crossbar & FIFOs */
generate
if (ao_spc_pkg::AO_SPC_NUM > 0) begin
if (AO_SPC_NUM_RND > 0) begin
/* Assign the bus port to the first input port of the AOPB */
reg_req_t [ao_spc_pkg::AO_SPC_NUM:0] packet_req;
reg_rsp_t [ao_spc_pkg::AO_SPC_NUM:0] packet_rsp;
reg_req_t [AO_SPC_NUM_RND:0] packet_req;
reg_rsp_t [AO_SPC_NUM_RND:0] packet_rsp;

assign packet_req[0] = peripheral_req;
assign peripheral_rsp = packet_rsp[0];

for (genvar i = 0; i < ao_spc_pkg::AO_SPC_NUM; i++) begin : gen_spc
for (genvar i = 0; i < AO_SPC_NUM_RND; i++) begin : gen_spc
assign packet_req[i+1] = spc2ao_req_i[i];
assign ao2spc_resp_o[i] = packet_rsp[i+1];
end

reg_mux #(
.NoPorts(ao_spc_pkg::AO_SPC_NUM + 1),
.NoPorts(AO_SPC_NUM_RND + 1),
.req_t (reg_pkg::reg_req_t),
.rsp_t (reg_pkg::reg_rsp_t),
.AW (32),
Expand Down
71 changes: 67 additions & 4 deletions hw/core-v-mini-mcu/core_v_mini_mcu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,16 @@
module core_v_mini_mcu
import obi_pkg::*;
import reg_pkg::*;
import ao_spc_pkg::*;
#(
parameter COREV_PULP = 0,
parameter FPU = 0,
parameter ZFINX = 0,
parameter EXT_XBAR_NMASTER = 0,
parameter X_EXT = 0, // eXtension interface in cv32e40x
parameter AO_SPC_NUM = 0,
parameter EXT_HARTS = 0,
//do not touch these parameters
parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT,
Expand Down Expand Up @@ -286,8 +287,8 @@ module core_v_mini_mcu
input obi_req_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_req_i,
output obi_resp_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_resp_o,

input reg_req_t ext_ao_peripheral_slave_req_i [ao_spc_pkg::AO_SPC_NUM-1:0],
output reg_rsp_t ext_ao_peripheral_slave_resp_o[ao_spc_pkg::AO_SPC_NUM-1:0],
input reg_req_t ext_ao_peripheral_slave_req_i [AO_SPC_NUM_RND-1:0],
output reg_rsp_t ext_ao_peripheral_slave_resp_o[AO_SPC_NUM_RND-1:0],

// External slave ports
output obi_req_t ext_core_instr_req_o,
Expand Down Expand Up @@ -458,6 +459,66 @@ module core_v_mini_mcu
assign memory_subsystem_banks_powergate_iso_n[1] = memory_subsystem_pwr_ctrl_out[1].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[1] = memory_subsystem_pwr_ctrl_out[1].retentive_en_n;
assign memory_subsystem_clkgate_en_n[1] = memory_subsystem_pwr_ctrl_out[1].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[2] = memory_subsystem_pwr_ctrl_out[2].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[2].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[2];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[2] = memory_subsystem_pwr_ctrl_out[2].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[2] = memory_subsystem_pwr_ctrl_out[2].retentive_en_n;
assign memory_subsystem_clkgate_en_n[2] = memory_subsystem_pwr_ctrl_out[2].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[3] = memory_subsystem_pwr_ctrl_out[3].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[3].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[3];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[3] = memory_subsystem_pwr_ctrl_out[3].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[3] = memory_subsystem_pwr_ctrl_out[3].retentive_en_n;
assign memory_subsystem_clkgate_en_n[3] = memory_subsystem_pwr_ctrl_out[3].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[4] = memory_subsystem_pwr_ctrl_out[4].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[4].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[4];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[4] = memory_subsystem_pwr_ctrl_out[4].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[4] = memory_subsystem_pwr_ctrl_out[4].retentive_en_n;
assign memory_subsystem_clkgate_en_n[4] = memory_subsystem_pwr_ctrl_out[4].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[5] = memory_subsystem_pwr_ctrl_out[5].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[5].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[5];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[5] = memory_subsystem_pwr_ctrl_out[5].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[5] = memory_subsystem_pwr_ctrl_out[5].retentive_en_n;
assign memory_subsystem_clkgate_en_n[5] = memory_subsystem_pwr_ctrl_out[5].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[6] = memory_subsystem_pwr_ctrl_out[6].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[6].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[6];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[6] = memory_subsystem_pwr_ctrl_out[6].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[6] = memory_subsystem_pwr_ctrl_out[6].retentive_en_n;
assign memory_subsystem_clkgate_en_n[6] = memory_subsystem_pwr_ctrl_out[6].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[7] = memory_subsystem_pwr_ctrl_out[7].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[7].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[7];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[7] = memory_subsystem_pwr_ctrl_out[7].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[7] = memory_subsystem_pwr_ctrl_out[7].retentive_en_n;
assign memory_subsystem_clkgate_en_n[7] = memory_subsystem_pwr_ctrl_out[7].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[8] = memory_subsystem_pwr_ctrl_out[8].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[8].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[8];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[8] = memory_subsystem_pwr_ctrl_out[8].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[8] = memory_subsystem_pwr_ctrl_out[8].retentive_en_n;
assign memory_subsystem_clkgate_en_n[8] = memory_subsystem_pwr_ctrl_out[8].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[9] = memory_subsystem_pwr_ctrl_out[9].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[9].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[9];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[9] = memory_subsystem_pwr_ctrl_out[9].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[9] = memory_subsystem_pwr_ctrl_out[9].retentive_en_n;
assign memory_subsystem_clkgate_en_n[9] = memory_subsystem_pwr_ctrl_out[9].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[10] = memory_subsystem_pwr_ctrl_out[10].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[10].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[10];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[10] = memory_subsystem_pwr_ctrl_out[10].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[10] = memory_subsystem_pwr_ctrl_out[10].retentive_en_n;
assign memory_subsystem_clkgate_en_n[10] = memory_subsystem_pwr_ctrl_out[10].clkgate_en_n;
assign memory_subsystem_banks_powergate_switch_n[11] = memory_subsystem_pwr_ctrl_out[11].pwrgate_en_n;
assign memory_subsystem_pwr_ctrl_in[11].pwrgate_ack_n = memory_subsystem_banks_powergate_switch_ack_n[11];
//isogate exposed outside for UPF sim flow and switch cells
assign memory_subsystem_banks_powergate_iso_n[11] = memory_subsystem_pwr_ctrl_out[11].isogate_en_n;
assign memory_subsystem_banks_set_retentive_n[11] = memory_subsystem_pwr_ctrl_out[11].retentive_en_n;
assign memory_subsystem_clkgate_en_n[11] = memory_subsystem_pwr_ctrl_out[11].clkgate_en_n;

for (genvar i = 0; i < EXT_DOMAINS_RND; i = i + 1) begin
assign external_subsystem_powergate_switch_no[i] = external_subsystem_pwr_ctrl_out[i].pwrgate_en_n;
Expand Down Expand Up @@ -619,7 +680,9 @@ module core_v_mini_mcu
.set_retentive_ni(memory_subsystem_banks_set_retentive_n)
);

ao_peripheral_subsystem ao_peripheral_subsystem_i (
ao_peripheral_subsystem #(
.AO_SPC_NUM(AO_SPC_NUM)
) ao_peripheral_subsystem_i (
.clk_i,
.rst_ni(rst_ni && debug_reset_n),
.slave_req_i(ao_peripheral_slave_req),
Expand Down
11 changes: 7 additions & 4 deletions hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,16 @@
module core_v_mini_mcu
import obi_pkg::*;
import reg_pkg::*;
import ao_spc_pkg::*;
#(
parameter COREV_PULP = 0,
parameter FPU = 0,
parameter ZFINX = 0,
parameter EXT_XBAR_NMASTER = 0,
parameter X_EXT = 0, // eXtension interface in cv32e40x
parameter AO_SPC_NUM = 0,
parameter EXT_HARTS = 0,
//do not touch these parameters
parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT,
Expand All @@ -40,8 +41,8 @@ ${pad.core_v_mini_mcu_interface}
input obi_req_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_req_i,
output obi_resp_t [EXT_XBAR_NMASTER_RND-1:0] ext_xbar_master_resp_o,

input reg_req_t ext_ao_peripheral_slave_req_i[ao_spc_pkg::AO_SPC_NUM-1:0],
output reg_rsp_t ext_ao_peripheral_slave_resp_o[ao_spc_pkg::AO_SPC_NUM-1:0],
input reg_req_t ext_ao_peripheral_slave_req_i[AO_SPC_NUM_RND-1:0],
output reg_rsp_t ext_ao_peripheral_slave_resp_o[AO_SPC_NUM_RND-1:0],

// External slave ports
output obi_req_t ext_core_instr_req_o,
Expand Down Expand Up @@ -369,7 +370,9 @@ ${pad.core_v_mini_mcu_interface}
.set_retentive_ni(memory_subsystem_banks_set_retentive_n)
);

ao_peripheral_subsystem ao_peripheral_subsystem_i (
ao_peripheral_subsystem #(
.AO_SPC_NUM(AO_SPC_NUM)
) ao_peripheral_subsystem_i (
.clk_i,
.rst_ni(rst_ni && debug_reset_n),
.slave_req_i(ao_peripheral_slave_req),
Expand Down
16 changes: 0 additions & 16 deletions hw/core-v-mini-mcu/include/ao_spc_pkg.sv
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This file was deleted.

1 change: 0 additions & 1 deletion hw/core-v-mini-mcu/include/x-heep_packages.core
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Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@ filesets:
- reg_pkg.sv
- power_manager_pkg.sv
- core_v_mini_mcu_pkg.sv
- ao_spc_pkg.sv
file_type: systemVerilogSource

targets:
Expand Down
8 changes: 5 additions & 3 deletions hw/system/x_heep_system.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -5,14 +5,15 @@
module x_heep_system
import obi_pkg::*;
import reg_pkg::*;
import ao_spc_pkg::*;
#(
parameter COREV_PULP = 0,
parameter FPU = 0,
parameter ZFINX = 0,
parameter EXT_XBAR_NMASTER = 0,
parameter X_EXT = 0, // eXtension interface in cv32e40x
parameter AO_SPC_NUM = 0,
//do not touch these parameters
parameter AO_SPC_NUM_RND = AO_SPC_NUM == 0 ? 1 : AO_SPC_NUM,
parameter EXT_XBAR_NMASTER_RND = EXT_XBAR_NMASTER == 0 ? 1 : EXT_XBAR_NMASTER,
parameter EXT_DOMAINS_RND = core_v_mini_mcu_pkg::EXTERNAL_DOMAINS == 0 ? 1 : core_v_mini_mcu_pkg::EXTERNAL_DOMAINS,
parameter NEXT_INT_RND = core_v_mini_mcu_pkg::NEXT_INT == 0 ? 1 : core_v_mini_mcu_pkg::NEXT_INT
Expand All @@ -37,8 +38,8 @@ module x_heep_system
output obi_req_t ext_dma_addr_req_o[core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0],
input obi_resp_t ext_dma_addr_resp_i[core_v_mini_mcu_pkg::DMA_NUM_MASTER_PORTS-1:0],

input reg_req_t ext_ao_peripheral_req_i[ao_spc_pkg::AO_SPC_NUM-1:0],
output reg_rsp_t ext_ao_peripheral_resp_o[ao_spc_pkg::AO_SPC_NUM-1:0],
input reg_req_t ext_ao_peripheral_req_i[AO_SPC_NUM_RND-1:0],
output reg_rsp_t ext_ao_peripheral_resp_o[AO_SPC_NUM_RND-1:0],

output reg_req_t ext_peripheral_slave_req_o,
input reg_rsp_t ext_peripheral_slave_resp_i,
Expand Down Expand Up @@ -119,6 +120,7 @@ ${pad.internal_signals}
.ZFINX(ZFINX),
.EXT_XBAR_NMASTER(EXT_XBAR_NMASTER),
.X_EXT(X_EXT),
.AO_SPC_NUM(AO_SPC_NUM),
.EXT_HARTS(EXT_HARTS)
) core_v_mini_mcu_i (

Expand Down
2 changes: 2 additions & 0 deletions tb/tb_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ module tb_top #(
parameter ZFINX = 0,
parameter JTAG_DPI = 0,
parameter X_EXT = 0,
parameter AO_SPC_NUM = 1,
parameter USE_EXTERNAL_DEVICE_EXAMPLE = 1
);

Expand Down Expand Up @@ -195,6 +196,7 @@ module tb_top #(
.FPU (FPU),
.ZFINX (ZFINX),
.X_EXT (X_EXT),
.AO_SPC_NUM (AO_SPC_NUM),
.JTAG_DPI (JTAG_DPI),
.USE_EXTERNAL_DEVICE_EXAMPLE(USE_EXTERNAL_DEVICE_EXAMPLE),
.CLK_FREQUENCY (CLK_FREQUENCY_KHz)
Expand Down
6 changes: 3 additions & 3 deletions tb/testharness.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ module testharness #(
parameter FPU = 0,
parameter ZFINX = 0,
parameter X_EXT = 0, // eXtension interface in cv32e40x
parameter AO_SPC_NUM = 1,
parameter JTAG_DPI = 0,
parameter USE_EXTERNAL_DEVICE_EXAMPLE = 1,
parameter CLK_FREQUENCY = 'd100_000 //KHz
Expand Down Expand Up @@ -46,7 +47,6 @@ module testharness #(

import obi_pkg::*;
import reg_pkg::*;
import ao_spc_pkg::*;
import testharness_pkg::*;
import addr_map_rule_pkg::*;
import core_v_mini_mcu_pkg::*;
Expand Down Expand Up @@ -152,8 +152,8 @@ module testharness #(
) ext_if ();

// External SPC interface signals
reg_req_t ext_ao_peripheral_req[ao_spc_pkg::AO_SPC_NUM-1:0];
reg_rsp_t ext_ao_peripheral_resp[ao_spc_pkg::AO_SPC_NUM-1:0];
reg_req_t ext_ao_peripheral_req[AO_SPC_NUM-1:0];
reg_rsp_t ext_ao_peripheral_resp[AO_SPC_NUM-1:0];

logic [core_v_mini_mcu_pkg::DMA_CH_NUM-1:0] dma_busy;

Expand Down

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