fix style of spi slave

esl-epfl · Jan 10, 2025 · ffe1f56 · ffe1f56
1 parent 4ef8b04
commit ffe1f56
Show file tree

Hide file tree

Showing 11 changed files with 25 additions and 45 deletions.
diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core
@@ -36,7 +36,7 @@ filesets:
     - x-heep:ip:fast_intr_ctrl
     - x-heep:ip:obi_fifo
     - x-heep:ip:pdm2pcm
-    - x-heep:ip:obi_spi_slave
+    - esl_epfl:ip:obi_spi_slave
     files:
     - hw/core-v-mini-mcu/core_v_mini_mcu.sv
     - hw/core-v-mini-mcu/cpu_subsystem.sv
@@ -95,7 +95,6 @@ filesets:
     - hw/system/x_heep_system.vlt
     - hw/simulation/simulation.vlt
     - hw/ip/i2s/i2s.vlt
-    - hw/ip/obi_spi_slave/obi_spi_slave.vlt
     file_type: vlt
 
   rtl-fpga:

diff --git a/hw/core-v-mini-mcu/core_v_mini_mcu.vlt b/hw/core-v-mini-mcu/core_v_mini_mcu.vlt
@@ -30,3 +30,4 @@ lint_off -rule WIDTH -file "*/ao_peripheral_subsystem.sv" -match "Input port con
 lint_off -rule UNDRIVEN -file "*ip/power_manager/rtl/power_manager.sv" -match "Signal is not driven: 'external_ram_banks_set_retentive*'"
 lint_off -rule UNDRIVEN -file "*ip/power_manager/rtl/power_manager.sv" -match "Signal is not driven: 'external_subsystem_clkgate_en*'"
 lint_off -rule UNUSED -file "*vendor/pulp_platform_register_interface/src/reg_mux.sv" -match "*"
+lint_off -rule UNUSED -file "*/core-v-mini-mcu/ao_peripheral_subsystem.sv" -match "Signal is not used: 'spi_slave_miso_i'*"
diff --git a/hw/system/x_heep_system.vlt b/hw/system/x_heep_system.vlt
@@ -8,3 +8,4 @@ lint_off -rule UNUSED -file "*/x_heep_system.sv" -match "*"
 lint_off -rule UNDRIVEN -file "*/x_heep_system.sv" -match "*"
 lint_off -rule DECLFILENAME -file "*pad_control_reg_top.sv" -match "Filename 'pad_control_reg_top' does not match MODULE name: 'pad_control_reg_top_intf'*"
 lint_off -rule DECLFILENAME -file "*soc_ctrl_reg_top.sv" -match "Filename 'soc_ctrl_reg_top' does not match MODULE name: 'soc_ctrl_reg_top_intf'*"
+lint_off -rule SYNCASYNCNET -file "*/system/x_heep_system.sv" -match "Signal flopped as both synchronous and async*"
diff --git a/hw/vendor/esl_epfl_obi_spi_slave.lock.hjson b/hw/vendor/esl_epfl_obi_spi_slave.lock.hjson
@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/esl-epfl/obi_spi_slave.git
-    rev: 8c517015c563559467ee90ba40ffb7365120b6a5
+    rev: bdc96513fbb7f5e6fd7938c24d311603bbfc5426
   }
 }
diff --git a/hw/vendor/esl_epfl_obi_spi_slave.vendor.hjson b/hw/vendor/esl_epfl_obi_spi_slave.vendor.hjson
@@ -7,7 +7,7 @@
 
   upstream: {
     url: "https://github.com/esl-epfl/obi_spi_slave.git",
-    rev: "8c517015c563559467ee90ba40ffb7365120b6a5",
+    rev: "bdc96513fbb7f5e6fd7938c24d311603bbfc5426",
   },
 
 

diff --git a/hw/vendor/pulp_platform_obi_spi_slave/obi_spi_slave.core b/hw/vendor/pulp_platform_obi_spi_slave/obi_spi_slave.core
@@ -1,9 +1,9 @@
 CAPI=2:
 
-name: "x-heep:ip:obi_spi_slave"
+name: "esl_epfl:ip:obi_spi_slave"
 description: "core-v-mini-mcu SPI2OBI peripheral"
 
-# Copyright 2021 OpenHW Group
+# Copyright 2024 EPFL
 # Solderpad Hardware License, Version 2.1, see LICENSE.md for details.
 # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
 
@@ -22,15 +22,6 @@ filesets:
     - spi_slave_syncro.sv
     - spi_slave_tx.sv
     file_type: systemVerilogSource
-
-  files_verilator_waiver:
-    depend:
-      # common waivers
-      - lowrisc:lint:common
-      - lowrisc:lint:comportable
-    files:
-      - obi_spi_slave.vlt
-    file_type: vlt
 
 targets:
   default:

diff --git a/hw/vendor/pulp_platform_obi_spi_slave/obi_spi_slave.sv b/hw/vendor/pulp_platform_obi_spi_slave/obi_spi_slave.sv
@@ -11,8 +11,7 @@
 module obi_spi_slave #(
 
     parameter OBI_ADDR_WIDTH = 32,
-    parameter OBI_DATA_WIDTH = 32,
-    parameter DUMMY_CYCLES   = 32
+    parameter OBI_DATA_WIDTH = 32
 ) (
     //input  logic test_mode,
     input  logic spi_sclk,
@@ -38,6 +37,8 @@ module obi_spi_slave #(
     input logic [OBI_DATA_WIDTH-1:0] obi_master_r_data
 );
 
+  localparam DUMMY_CYCLES = 32;
+
   logic [               7:0] rx_counter;
   logic                      rx_counter_upd;
   logic [              31:0] rx_data;
@@ -55,9 +56,7 @@ module obi_spi_slave #(
 
   logic [              31:0] ctrl_data_rx;
   logic                      ctrl_data_rx_valid;
-  logic                      ctrl_data_rx_ready;
   logic [              31:0] ctrl_data_tx;
-  logic                      ctrl_data_tx_valid;
   logic                      ctrl_data_tx_ready;
 
   logic [              31:0] fifo_data_rx;
@@ -100,7 +99,7 @@ module obi_spi_slave #(
   );
 
   spi_slave_controller #(
-      .DUMMY_CYCLES(DUMMY_CYCLES)
+    .DUMMY_CYCLES(DUMMY_CYCLES)
   ) u_slave_sm (
       .sclk              (spi_sclk),
       .sys_rstn          (obi_aresetn),
@@ -125,14 +124,13 @@ module obi_spi_slave #(
   );
 
   spi_slave_dc_fifo #(
-      .DATA_WIDTH  (32),
-      .BUFFER_DEPTH(8)
+      .DATA_WIDTH  (32)
   ) u_dcfifo_rx (
       .clk_a  (spi_sclk),
       .rstn_a (obi_aresetn),
       .data_a (ctrl_data_rx),
       .valid_a(ctrl_data_rx_valid),
-      .ready_a(ctrl_data_rx_ready),
+      .ready_a(),
       .clk_b  (obi_aclk),
       .rstn_b (obi_aresetn),
       .data_b (fifo_data_rx),
@@ -141,8 +139,7 @@ module obi_spi_slave #(
   );
 
   spi_slave_dc_fifo #(
-      .DATA_WIDTH  (32),
-      .BUFFER_DEPTH(8)
+      .DATA_WIDTH  (32)
   ) u_dcfifo_tx (
       .clk_a  (obi_aclk),
       .rstn_a (obi_aresetn),
@@ -152,7 +149,7 @@ module obi_spi_slave #(
       .clk_b  (spi_sclk),
       .rstn_b (obi_aresetn),
       .data_b (ctrl_data_tx),
-      .valid_b(ctrl_data_tx_valid),
+      .valid_b(),
       .ready_b(ctrl_data_tx_ready)
   );
 

diff --git a/hw/vendor/pulp_platform_obi_spi_slave/obi_spi_slave.vlt b/hw/vendor/pulp_platform_obi_spi_slave/obi_spi_slave.vlt
diff --git a/hw/vendor/pulp_platform_obi_spi_slave/spi_slave_controller.sv b/hw/vendor/pulp_platform_obi_spi_slave/spi_slave_controller.sv
@@ -10,7 +10,7 @@
 
 
 module spi_slave_controller #(
-    parameter DUMMY_CYCLES = 32
+  parameter DUMMY_CYCLES = 32
 ) (
     input  logic        sclk,
     input  logic        sys_rstn,
@@ -88,7 +88,8 @@ module spi_slave_controller #(
   );
 
   spi_slave_regs #(
-      .REG_SIZE(REG_SIZE)
+      .REG_SIZE(REG_SIZE),
+      .DUMMY_CYCLES(DUMMY_CYCLES)
   ) u_spiregs (
       .sclk(sclk),
       .rstn(sys_rstn),
@@ -200,6 +201,9 @@ module spi_slave_controller #(
           state_next = DATA_TX;
         end
       end
+      default: begin
+        state_next = state;
+      end
     endcase
   end
 

diff --git a/hw/vendor/pulp_platform_obi_spi_slave/spi_slave_dc_fifo.sv b/hw/vendor/pulp_platform_obi_spi_slave/spi_slave_dc_fifo.sv
@@ -9,8 +9,7 @@
 // specific language governing permissions and limitations under the License.
 
 module spi_slave_dc_fifo #(
-    parameter DATA_WIDTH   = 32,
-    parameter BUFFER_DEPTH = 8
+    parameter DATA_WIDTH   = 32
 ) (
     input logic clk_a,
     input logic rstn_a,

diff --git a/hw/vendor/pulp_platform_obi_spi_slave/spi_slave_regs.sv b/hw/vendor/pulp_platform_obi_spi_slave/spi_slave_regs.sv
@@ -9,7 +9,8 @@
 // specific language governing permissions and limitations under the License.
 
 module spi_slave_regs #(
-    parameter REG_SIZE = 8
+    parameter REG_SIZE = 8,
+    parameter DUMMY_CYCLES = 32
 ) (
     input  logic                sclk,
     input  logic                rstn,
@@ -41,7 +42,7 @@ module spi_slave_regs #(
 
   always @(posedge sclk or negedge rstn) begin
     if (rstn == 0) begin
-      reg0 <= 'd32;
+      reg0 <= DUMMY_CYCLES;
       reg1 <= 'h0;
       reg2 <= 'h0;
     end else begin