fix: default uart tx_idle_num to 0 (#2859)

* feat: uart configurable `tx_idle_num` * fix: remove extraneous setter * fix: use `ConfigError` instead of `assert!`; clarify unit of bit time * fix: remove unneeded assert * chore: revert by updating to newest main * fix: just set to 0 * fix: unsafe on the register modification * Fix changelog --------- Co-authored-by: Dániel Buga <[email protected]>
esp-rs · Jan 21, 2025 · 9e4cbbd · 9e4cbbd
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diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -19,6 +19,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Uart `flush` is now blocking (#2882)
 - Removed `embedded-hal-nb` traits (#2882)
 - `timer::wait` is now blocking (#2882)
+- By default, set `tx_idle_num` to 0 so that bytes written to TX FIFO are always immediately transmitted. (#2859)
 
 - `Rng` and `Trng` now implement `Peripheral<P = Self>` (#2992)
 

diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
@@ -1223,6 +1223,12 @@ where
 
         self.rx.uart.info().apply_config(&config)?;
 
+        // Don't wait after transmissions by default,
+        // so that bytes written to TX FIFO are always immediately transmitted.
+        self.register_block()
+            .idle_conf()
+            .modify(|_, w| unsafe { w.tx_idle_num().bits(0) });
+
         // Setting err_wr_mask stops uart from storing data when data is wrong according
         // to reference manual
         self.register_block()