Updated PDP11 clock to 32 MHz; final 0.19 firmware prior to bumping v…

…ersion to 0.20 Change-Id: I38298cb50c4829a160531241082581f00df26cbe
hoglet67 · Aug 14, 2015 · 82032a0 · 82032a0
1 parent c7284cb
commit 82032a0
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Showing 2 changed files with 7 additions and 28 deletions.
diff --git a/LX9Co-PDP11.xise b/LX9Co-PDP11.xise
@@ -43,7 +43,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="src/LX9Co_CoProPDP11.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="src/Tube/ph_fifo.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
@@ -57,10 +57,6 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
-    <file xil_pn:name="src/DCM/dcm_32_16.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
-    </file>
     <file xil_pn:name="src/ROM/tuberom_pdp11.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>

diff --git a/src/LX9Co_CoProPDP11.vhd b/src/LX9Co_CoProPDP11.vhd
@@ -36,7 +36,6 @@ architecture BEHAVIORAL of LX9CoProPDP11 is
 -- clock and reset signals
 -------------------------------------------------
 
-    signal clk_16M00     : std_logic;
     signal clk_cpu       : std_logic;
     signal clk_ram       : std_logic;
     signal clk_tube      : std_logic;
@@ -92,16 +91,9 @@ begin
 -- instantiated components
 ---------------------------------------------------------------------
 
-    inst_dcm_32_16 : entity work.dcm_32_16 port map (
-        CLKIN_IN  => fastclk,
-        CLK0_OUT  => clk_16M00,
-        CLK0_OUT1 => open,
-        CLK2X_OUT => open
-    );
-
 
     inst_tuberom : entity work.tuberom_pdp11 port map (
-        CLK             => clk_16M00,
+        CLK             => clk_ram,
         ADDR            => cpu_addr(10 downto 1),
         DATA            => rom_data_out
     );
@@ -243,8 +235,6 @@ begin
 --    test(3) <= cpu_din(2);
 --    test(2) <= cpu_din(1);
 --    test(1) <= cpu_din(0);
-
-
 
     test(8) <= '1' when ifetch = '1' and cpu_addr = o"176320" else '0';
     test(7) <= '1' when ifetch = '1' and cpu_addr = o"176404" else '0';
@@ -255,26 +245,19 @@ begin
     test(2) <= '1' when ifetch = '1' and cpu_addr = x"0000"   else '0';
     test(1) <= cpu_IRQ_n;
 
---    
 --------------------------------------------------------
 -- clock enable generator
 --------------------------------------------------------
-    clk_gen : process(clk_16M00, RSTn)
-    begin
-        if rising_edge(clk_16M00) then
-            clken_counter <= clken_counter + 1;
-            clk_cpu       <= not clken_counter(0);
-            clk_tube      <= not clken_counter(0);
-            clk_ram       <= clk_cpu;
-        end if;
-    end process;
+    clk_cpu       <= fastclk;
+    clk_tube      <= fastclk;
+    clk_ram       <= not fastclk;
 
 --------------------------------------------------------
 -- power up reset
 --------------------------------------------------------
-    reset_gen : process(clk_16M00)
+    reset_gen : process(clk_cpu)
     begin
-        if rising_edge(clk_16M00) then
+        if rising_edge(clk_cpu) then
             if (reset_counter(8) = '0') then
                 reset_counter <= reset_counter + 1;
             end if;