Skip to content
/ riscV Public

This represents a CS-students project of creating a RV-core.

Notifications You must be signed in to change notification settings

jjjt-git/riscV

Repository files navigation

riscV

summary

This is a simple RV32I-Core, I am creating as a side project parallel to my university education in computer science.

aims

This project does not aim to be an efficient RiscV-core, but to allow me to learn about processor design. This means, that while you are welcome to fork and modify my core, I will not merge pull-requests, as long as I activly modify it. Issues with tips are (of course) appreciated.

building

The Makefile is designed to be used with ghdl. Use make run to execute all testbenches, creating ghw-files of the runs for use with gtkwave.

About

This represents a CS-students project of creating a RV-core.

Topics

Resources

Stars

Watchers

Forks

Packages

No packages published