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colorlight_5a_75x: Disable full_memory_we for l2 cache by default #250

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merged 1 commit into from
Aug 11, 2021

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david-sawatzke
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Leads to an increase in DP16KD usage, first noticed in enjoy-digital/liteeth#70.
With full_mem_we:

Info: 	              DP16KD:    41/   56    73%

Without:

Info: 	              DP16KD:    29/   56    51%

Might also be relevant for other yosys/ecp5 targets.

Versions:
Yosys 0.9+4241 (git sha1 8733e1923, gcc 11.1.0 -march=native -mtune=generic -O2 -fno-plt -fPIC -Os)
nextpnr-ecp5 -- Next Generation Place and Route (Version ef1fbfc6)

Command:

python colorlight_5a_75x.py --build

Leads to an increase in DP16KD, first noticed in
enjoy-digital/liteeth#70.
With full_mem_we:
```
Info: 	              DP16KD:    41/   56    73%
```
Without:
```
Info: 	              DP16KD:    29/   56    51%
```
@enjoy-digital enjoy-digital merged commit b77b151 into litex-hub:master Aug 11, 2021
@enjoy-digital
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Thanks @david-sawatzke, this is merged.

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2 participants