1.6

src/2306/baseline/1.6.md

@@ -84,6 +84,6 @@ RISC-V完整的异常处理机制远比我们现在实现的复杂,
 The complete exception handling mechanism in RISC-V is far more complex than what we are currently implementing.
 Commercial RISC-V processors must accurately implement every detail described in the manual, regardless of whether customers will use it. 
 Implementing all CSRs and meticulously detailing every bit is actually an engineering-intensive task that requires a lot of effort from the engineering team.
-However, "One Student, One Chip" is ultimately an educational project. The goal is not to design a RISC-V processor that meets commercial delivery requirements. 
+However, "OSOC" is ultimately an educational project. The goal is not to design a RISC-V processor that meets commercial delivery requirements. 
 Therefore, we can simplify various complex mechanisms under the premise of correctly running demonstration programs, allowing everyone to focus on learning key principles and developing core functionality.
 As we run more programs in Stage A in the future, we will gradually add various CSRs and their core functionalities.