Merge pull request openhwgroup#167 from XavierAubert/cv32e40p/xau_fix

shell script generation now correclty supports multiple test_cfg file…
pascalgouedo · Feb 27, 2024 · f31875d · f31875d
2 parents e833720 + 2f8545e
commit f31875d
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Showing 6 changed files with 34 additions and 22 deletions.
diff --git a/bin/lib/cv_regression.py b/bin/lib/cv_regression.py
@@ -89,9 +89,6 @@ def __init__(self, **kwargs):
         if not hasattr(self, 'testname'):
             self.testname = self.name
 
-        if not hasattr(self, 'riscvdv_cfg'):
-            self.riscvdv_cfg = ''
-
         # Log equals the test name if does not exist
         if not hasattr(self, 'log'):
             self.log = self.name

diff --git a/bin/templates/regress_sh.j2 b/bin/templates/regress_sh.j2
@@ -105,8 +105,12 @@ popd > /dev/null
 {% else %}
   {% set test_cfg = "" %}
 {% endif %}
+{% set test_cfg_list = test_cfg|replace(" ",",")|replace("+",",") %}
+{% set test_cfg_list = test_cfg_list.split(",")|unique|sort %}
+{% set test_cfg_path = test_cfg_list|join("__") %}
+
 # --> Test (Index: {{run_index}}): {{t.cmd}} : {{t.description}}
-{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1' + ' RISCVDV_CFG=' + t.riscvdv_cfg + ' SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=' + test_cfg + ' ' + regress_macros.cv_results(results) + ' ' + makeargs %}
+{% set cmd = test_cmd + ' CV_CORE=' + project + ' CFG=' + r.builds[build].cfg + ' ' + toolchain|upper + '=1 SIMULATOR=' + t.simulator + ' COMP=0 USE_ISS=' + regress_macros.yesorno(t.iss) + ' COV=' + regress_macros.yesorno(t.cov) + ' SEED=random GEN_START_INDEX=' + run_index|string + ' RUN_INDEX=' + run_index|string + ' TEST_CFG_FILE=\"' + test_cfg + '\" ' + regress_macros.cv_results(results) + ' ' + makeargs %}
 echo "{{session}}: Running test [cd {{t.abs_dir}} && {{cmd}}]"
 pushd {{t.abs_dir}} > /dev/null
 {{cmd}} >& /dev/null;
@@ -118,13 +122,7 @@ popd > /dev/null
 {% else %}
 {% set results_dir = t.simulator + '_results' %}
 {% endif %}
-{% if t.test_cfg is defined %}
-  {% set sim_log = t.simulator + '-' + test_log + '_' + t.test_cfg + '.log' %}
-  {% set test_cfg_path = t.test_cfg %}
-{% else %}
-  {% set sim_log = t.simulator + '-' + test_log + '.log' %}
-  {% set test_cfg_path = '' %}
-{% endif %}
+{% set sim_log = t.simulator + '-' + test_log + '.log' %}
 
 {# Determine log location #}
 {% if t.results %}

diff --git a/bin/templates/regress_vsif.j2 b/bin/templates/regress_vsif.j2
@@ -64,7 +64,7 @@ group {{project}} {
         test precmd {
             sv_seed: gen_random;
             count: 1;
-            run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} RISCVDV_CFG={{t.riscvdv_cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}';
+            run_script: 'cd {{t.abs_dir}} && {{t.precmd}} CV_SIM_PREFIX= CV_CORE={{project}} CFG={{build.cfg}} {{toolchain|upper}}=1 SIMULATOR={{t.simulator}} RNDSEED=$RUN_ENV(BRUN_SV_SEED) NUM_TESTS={{t.num}} {{regress_macros.cv_results(results)}} {{makeargs}}';
         };
 {% else %}
 {% endif %}

diff --git a/cv32e40p/regress/README.md b/cv32e40p/regress/README.md
@@ -0,0 +1,26 @@
+CV32E40P Regress Files
+==================================
+
+For V2 core, all the regressions files should be generated using the following cv_regress commands, where *type* has to be chosen between `sh` and `rmdb`, and *sim* is the wanted simulator (vsim, xrun, ...)
+
+## pulp configuration
+
+> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp.{type} --cfg pulp <br>
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp.{type} --cfg pulp<br>
+
+## pulp_fpu configuration
+> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en<br>
+> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en<br>
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu.{type} --cfg pulp_fpu --add_test_cfg floating_pt_instr_en<br>
+
+## pulp_fpu_zfinx configuration
+> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en<br>
+> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en<br>
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx.{type} --cfg pulp_fpu_zfinx --add_test_cfg floating_pt_zfinx_instr_en<br>
+
+## configurations with latency
+To generate regressions with latency (e.g. pulp_fpu_zfinx_2cyclat), only the `--cfg` switch has to be updated:
+
+> ./cv_regress --{type} --file=cv32e40pv2_xpulp_instr.yaml --simulator={sim} --outfile=xpulp_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_zfinx_instr_en<br>
+> ./cv_regress --{type} --file=cv32e40pv2_fpu_instr.yaml --simulator={sim} --outfile=fpu_instr_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en<br>
+> ./cv_regress --{type} --file=cv32e40pv2_interrupt_debug.yaml --simulator={sim} --outfile=int_debug_pulp_fpu_zfinx_2cyclat.{type} --cfg pulp_fpu_zfinx_2cyclat --add_test_cfg floating_pt_instr_en
diff --git a/mk/Common.mk b/mk/Common.mk
@@ -191,16 +191,9 @@ ifneq ($(filter gen_corev-dv,$(MAKECMDGOALS)),)
 ifeq ($(TEST),)
 $(error ERROR must specify a TEST variable with gen_corev-dv target)
 endif
-ifeq ($(RISCVDV_CFG),)
 GEN_FLAGS_MAKE := $(shell $(YAML2MAKE) --test=$(TEST) --yaml=corev-dv.yaml $(YAML2MAKE_DEBUG) --prefix=GEN --core=$(CV_CORE))
 ifeq ($(GEN_FLAGS_MAKE),)
-$(error ERROR Could not find corev-dv.yaml of for test: $(TEST))
-endif
-else
-GEN_FLAGS_MAKE := $(shell $(YAML2MAKE) --test=$(TEST) --yaml=$(RISCVDV_CFG).yaml $(YAML2MAKE_DEBUG) --prefix=GEN --core=$(CV_CORE))
-ifeq ($(GEN_FLAGS_MAKE),)
-$(error ERROR Could not find corev-dv_$(RISCVDV_CFG).yaml of for test: $(TEST))
-endif
+$(error ERROR Could not find corev-dv.yaml for test: $(TEST))
 endif
 include $(GEN_FLAGS_MAKE)
 endif

diff --git a/mk/uvmt/uvmt.mk b/mk/uvmt/uvmt.mk
@@ -169,8 +169,6 @@ export RISCV_DV_ROOT         = $(RISCVDV_PKG)
 export COREV_DV_ROOT         = $(COREVDV_PKG)
 export CV_CORE_COREV_DV_ROOT = $(CV_CORE_COREVDV_PKG)
 
-RISCVDV_CFG ?=
-
 # EMBench benchmarking suite
 EMBENCH_PKG	:= $(CORE_V_VERIF)/$(CV_CORE_LC)/vendor_lib/embench
 EMBENCH_TESTS	:= $(CORE_V_VERIF)/$(CV_CORE_LC)/tests/programs/embench