Merge pull request openhwgroup#220 from XavierAubert/cv32e40p/dev_dd_pgo

Slight change for better RTL coverage.
pascalgouedo · Apr 8, 2024 · f79204d · f79204d
2 parents 8b29ba9 + 452daaf
commit f79204d
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Showing 2 changed files with 7 additions and 6 deletions.
diff --git a/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml b/cv32e40p/regress/cv32e40pv2_xpulp_instr.yaml
@@ -88,12 +88,12 @@ tests:
     build: uvmt_cv32e40p
     description: pulp_hardware_loop directed test
     dir: cv32e40p/sim/uvmt
-    cmd: make test COREV=YES TEST=pulp_hardware_loop CFG_PLUSARGS="+UVM_TIMEOUT=1000000" VSIM_USER_FLAGS=+skip_sampling_uvme_rv32x_hwloop_covg
+    cmd: make test COREV=YES TEST=pulp_hardware_loop CFG_PLUSARGS="+UVM_TIMEOUT=1000000" VSIM_USER_FLAGS="+skip_sampling_uvme_rv32x_hwloop_covg +fixed_data_gnt_stall=3"
     num: 1
 
   pulp_hardware_loop_interrupt_test:
     build: uvmt_cv32e40p
-    description: pulp_hardware_loop directed test
+    description: pulp_hardware_loop_interrupt_test directed test
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=pulp_hardware_loop_interrupt_test CFG_PLUSARGS="+UVM_TIMEOUT=1000000"
     num: 1
@@ -136,7 +136,7 @@ tests:
 
   pulp_hardware_loop_debug_test:
     build: uvmt_cv32e40p
-    description: pulp_hardware_loop directed test
+    description: pulp_hardware_loop_debug_test directed test
     dir: cv32e40p/sim/uvmt
     cmd: make test COREV=YES TEST=pulp_hardware_loop_debug_test
     num: 1

diff --git a/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S b/cv32e40p/tests/programs/custom/pulp_hardware_loop/pulp_hardware_loop.S
@@ -315,7 +315,6 @@ test6_5:
     beq x20, x10, test7
     c.addi x15, 0x1
 
-
 # test7 CSR read accesses during HWloop (same as test1 but with CSR reads to mstatus)
 
 test7:
@@ -327,6 +326,8 @@ test7:
     li x8, 0
     li x17, 0
     li x18, 0
+    li x30, 0x80
+    li x31, 0
 
     .balign 4
 
@@ -345,7 +346,7 @@ startZ_7:
     addi x17, x17, 1
     csrr x5, 0x300 # mstatus
     addi x17, x17, 1
-    addi x17, x17, 1
+    lw x31, 0(x30)
     csrr x6, 0x300 # mstatus
 endZ_7:
     addi x18, x18, 1
@@ -356,7 +357,7 @@ endO_7:
 
     .option rvc
 
-    li x20, 300
+    li x20, 200
     beq x20, x17, test7_1
     c.addi x15, 0x1
 test7_1: