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Lane 的实现 #1

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Lane 的实现 #1

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qinjun-li
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@qinjun-li qinjun-li marked this pull request as ready for review July 6, 2022 07:31
@sequencer sequencer marked this pull request as draft July 6, 2022 08:19
import chisel3._
import chisel3.util._

case class LaneDivParameter(dataWidth: Int, maskWidth: Int)
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maskWidth 不存在


import chisel3._
import chisel3.util._
import freechips.rocketchip.util.{OH1ToUInt, leftOR}
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使用 chisel 标准库的实现

val resp: UInt = IO(Output(UInt(param.ELEN.W)))

resp := VecInit(src.map(_.asBools).transpose.map { case Seq(sr0, sr1) =>
val bitCalculate = Module(new LaneBitLogic)
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import chisel3._

class LaneMul(param: VectorParameters) extends Module {
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使用 LaneMulParameters

import chisel3._
import chisel3.util.PopCount

case class LanePopCountParameter(inputWidth: Int, outputWidth: Int)
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文档

import chisel3._
import chisel3.util._

case class LaneShifterParameter(dataWidth: Int, maskWidth: Int, shifterSizeBit: Int)
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需要再确定参数

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5 participants