WIP: litex: sim: Get sim working in litex-buildenv

.travis.yml

@@ -18,6 +18,8 @@ addons:
     - python-yaml
     - realpath
     - util-linux
+    - libevent-dev
+    - libjson-c-dev
 
 git:
   submodules: false
@@ -185,3 +187,13 @@ jobs:
 
   - stage: Targets
     env: C=lm32 P=opsis T="hdmi2usb"
+
+  #--------------------------------------------
+  # SIM/Verilator Targets
+  #--------------------------------------------
+  - stage: Targets
+    env: C=or1k P=sim T="base"
+
+  - stage: Targets
+    env: C=or1k P=sim T="base net"
+

gateware/firmware.py

@@ -6,34 +6,38 @@
 
 
 class MemoryMustHaveContents(Memory):
+    def load_init_data(self):
+        assert os.path.exists(self.filename), (
+            "ROM contents not found! {}".format(self.filename))
+
+        data = []
+        with open(self.filename, "rb") as firmware_file:
+            while True:
+                w = firmware_file.read(4)
+                if not w:
+                    break
+                data.append(struct.unpack(">I", w)[0])
+        data_size = len(data)*4
+        assert data_size > 0
+        assert data_size < self.size, (
+            "Firmware is too big! {} bytes > {} bytes".format(
+                data_size, self.size))
+        print("Firmware {} bytes ({} bytes left)".format(
+            data_size, self.size-data_size))
+
+        self.init = data
+
     @staticmethod
     def emit_verilog(memory, ns, add_data_file):
-        assert memory.init, "ROM contents not found! {}".format(memory.filename)
+        memory.load_init_data()
         return Memory.emit_verilog(memory, ns, add_data_file)
 
 
 class FirmwareROM(wishbone.SRAM):
     def __init__(self, size, filename):
-        if os.path.exists(filename):
-            data = []
-            with open(filename, "rb") as firmware_file:
-                while True:
-                    w = firmware_file.read(4)
-                    if not w:
-                        break
-                    data.append(struct.unpack(">I", w)[0])
-            data_size = len(data)*4
-            assert data_size > 0
-            assert data_size < size, (
-                "Firmware is too big! {} bytes > {} bytes".format(
-                    data_size, size))
-            print("Firmware {} bytes ({} bytes left)".format(
-                data_size, size-data_size))
-            wishbone.SRAM.__init__(self, size, init=data)
-        else:
-            print("No firmware found! ({}) Won't compile.".format(
-                filename))
-            wishbone.SRAM.__init__(self, size)
+        wishbone.SRAM.__init__(self, size)
 
+        # Switch the rom memory class to be able to lazy load contents.
         self.mem.__class__ = MemoryMustHaveContents
         self.mem.filename = filename
+        self.mem.size = size

platforms/sim.py

@@ -1,3 +1,64 @@
-from litex.boards.platforms import sim
-from litex.boards.platforms.sim import *
-__all__ = ['SimPins', 'Platform']
+from litex.build.generic_platform import *
+from litex.build.sim import SimPlatform
+
+from litex.build.sim.config import SimConfig
+
+class SimPins(Pins):
+    def __init__(self, n):
+        Pins.__init__(self, "s "*n)
+
+_io = [
+    ("sys_clk", 0, SimPins(1)),
+    ("sys_rst", 0, SimPins(1)),
+    ("serial", 0,
+        Subsignal("source_valid", SimPins(1)),
+        Subsignal("source_ready", SimPins(1)),
+        Subsignal("source_data", SimPins(8)),
+
+        Subsignal("sink_valid", SimPins(1)),
+        Subsignal("sink_ready", SimPins(1)),
+        Subsignal("sink_data", SimPins(8)),
+    ),
+    ("eth_clocks", 0,
+        Subsignal("none", SimPins(1)),
+    ),
+    ("eth", 0,
+        Subsignal("source_valid", SimPins(1)),
+        Subsignal("source_ready", SimPins(1)),
+        Subsignal("source_data", SimPins(8)),
+
+        Subsignal("sink_valid", SimPins(1)),
+        Subsignal("sink_ready", SimPins(1)),
+        Subsignal("sink_data", SimPins(8)),
+    ),
+    ("vga", 0,
+        Subsignal("de", SimPins(1)),
+        Subsignal("hsync", SimPins(1)),
+        Subsignal("vsync", SimPins(1)),
+        Subsignal("r", SimPins(8)),
+        Subsignal("g", SimPins(8)),
+        Subsignal("b", SimPins(8)),
+    ),
+]
+
+
+class Platform(SimPlatform):
+    default_clk_name = "sys_clk"
+    default_clk_period = 1000  # on modern computers simulate at ~ 1MHz
+
+    def __init__(self):
+        SimPlatform.__init__(self, "SIM", _io)
+
+    def do_finalize(self, fragment):
+        pass
+
+    def build(self, fragment, **kwargs):
+        scfg = SimConfig(default_clk="sys_clk")
+        scfg.add_module("serial2console", "serial")
+        if hasattr(fragment, 'remoteip'):
+            scfg.add_module('ethernet', "eth", args={ "interface": "tap0",
+                                                      "ip": fragment.remoteip })
+        kwargs['sim_config'] = scfg
+        # Do not run the simulator after we build it
+        kwargs['run'] = False
+        return SimPlatform.build(self, fragment, **kwargs)

scripts/download-env.sh

@@ -264,6 +264,14 @@ case $PLATFORM_TOOLCHAIN in
 		conda install -y $CONDA_FLAGS nextpnr
 		check_exists nextpnr-ice40
 		;;
+	Sim)
+		export HAVE_FPGA_TOOLCHAIN=1
+		# verilator
+		echo
+		echo "Installing verilator (Verilog Simulator tool)"
+		conda install -y $CONDA_FLAGS verilator
+		check_exists verilator
+		;;
 	*)
 		;;
 esac

scripts/enter-env.sh

@@ -251,6 +251,14 @@ case $PLATFORM_TOOLCHAIN in
 
 		check_exists nextpnr-ice40 || return 1
 		;;
+	Sim)
+		export HAVE_FPGA_TOOLCHAIN=1
+		# verilator
+
+
+
+		check_exists verilator || return 1
+		;;
 	*)
 		;;
 esac

targets/sim/Makefile.mk

@@ -46,26 +46,8 @@ bios-flash-$(PLATFORM):
 
 # Extra commands
 help-$(PLATFORM):
-	@echo " make $(PLATFORM)-setup"
-	@echo " make $(PLATFORM)-teardown"
+	@true
 
 reset-$(PLATFORM):
 	@echo "Unsupported."
 	@false
-
-$(PLATFORM)-setup:
-	sudo true
-	sudo openvpn --mktun --dev tap0
-	sudo ifconfig tap0 $(IPRANGE).100 up
-	sudo mknod /dev/net/tap0 c 10 200
-	sudo chown $(shell whoami) /dev/net/tap0
-	make tftpd_start
-
-$(PLATFORM)-teardown:
-	sudo true
-	make tftpd_stop
-	sudo rm -f /dev/net/tap0
-	sudo ifconfig tap0 down
-	sudo openvpn --rmtun --dev tap0
-
-.PHONY: $(PLATFORM)-setup $(PLATFORM)-teardown

targets/sim/base.py

@@ -1,4 +1,6 @@
 # Support for simulation via verilator
+import os
+
 from migen import *
 from migen.genlib.io import CRG
 
@@ -17,11 +19,6 @@
 
 
 class BaseSoC(SoCSDRAM):
-    csr_peripherals = (
-        ,
-    )
-    csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
-
     mem_map = {
         "firmware_ram": 0x20000000,  # (default shadow @0xa0000000)
     }
@@ -32,11 +29,17 @@ def __init__(self, platform, **kwargs):
             kwargs['integrated_rom_size']=0x8000
         if 'integrated_sram_size' not in kwargs:
             kwargs['integrated_sram_size']=0x8000
-        if 'firmware_ram_size' not in kwargs:
-            kwargs['firmware_ram_size']=0x10000
-        if 'firmware_filename' not in kwargs:
-            kwargs['firmware_filename'] = "build/sim_{}_{}/software/firmware/firmware.fbi".format(
-                self.__class__.__name__.lower()[:-3], kwargs.get('cpu_type', 'lm32'))
+
+        firmware_ram_size=0x20000
+
+        full_cpu = kwargs.get('cpu_type', 'lm32')
+        if 'cpu_variant' in kwargs:
+            full_cpu = "{}.{}".format(full_cpu, kwargs['cpu_variant'])
+
+        firmware_filename="{}/build/sim_{}_{}/software/firmware/firmware.fbi".format(
+                os.getcwd(),
+                self.__class__.__name__.lower()[:-3],
+                full_cpu)
 
         clk_freq = int((1/(platform.default_clk_period))*1000000000)
         SoCSDRAM.__init__(self, platform, clk_freq, with_uart=False, **kwargs)
@@ -76,5 +79,4 @@ def __init__(self, platform, **kwargs):
         self.add_constant("MEMTEST_ADDR_SIZE", 1024)
         self.add_constant("SIMULATION", 1)
 
-
 SoC = BaseSoC

targets/sim/net.py

@@ -22,7 +22,7 @@ class NetSoC(BaseSoC):
     csr_map.update(BaseSoC.csr_map)
 
     interrupt_map = {
-        "ethmac": 2,
+        "ethmac": 3,
     }
     interrupt_map.update(BaseSoC.interrupt_map)
 
@@ -43,14 +43,20 @@ def __init__(self, *args, **kwargs):
         self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
         self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
+        # Disable the flash boot address under the net target, so we boot from
+        # net
+        self.flash_boot_address = None
+
     def configure_iprange(self, iprange):
         iprange = [int(x) for x in iprange.split(".")]
         while len(iprange) < 4:
             iprange.append(0)
         # Our IP address
         self._configure_ip("LOCALIP", iprange[:-1]+[50])
         # IP address of tftp host
-        self._configure_ip("REMOTEIP", iprange[:-1]+[100])
+        remoteip = iprange[:-1]+[100]
+        self.remoteip = ".".join(map(str, remoteip))
+        self._configure_ip("REMOTEIP", remoteip)
 
     def _configure_ip(self, ip_type, ip):
         for i, e in enumerate(ip):