Merge pull request timvideos#493 from antmicro/mor1kx_external_dt

linux: mor1kx: Add support for the external DT
whatnick · Jul 22, 2020 · c4ca21c · c4ca21c
2 parents 8126cd4 + e4b13b4
commit c4ca21c
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Showing 8 changed files with 13 additions and 10 deletions.
diff --git a/Makefile b/Makefile
@@ -406,14 +406,14 @@ tftp: $(FIRMWARE_FILEBASE).bin
 
 ifeq ($(FIRMWARE),linux)
 	cp $(FIRMWARE_FILEBASE).bin $(TFTPD_DIR)/Image
+	cp $(FIRMWARE_DIR)/$(ROOTFS_FILE) $(TFTPD_DIR)/rootfs.cpio
 	cp $(FIRMWARE_DIR)/boot.json $(TFTPD_DIR)
 ifeq ($(CPU),vexriscv)
 	cp $(FIRMWARE_DIR)/rv32.dtb $(TFTPD_DIR)
 	cp $(TARGET_BUILD_DIR)/emulator/emulator.bin $(TFTPD_DIR)
-	cp $(FIRMWARE_DIR)/$(ROOTFS_FILE) $(TFTPD_DIR)/rootfs.cpio
 endif
 ifeq ($(CPU),mor1kx)
-        # ATM nothing, DTB in the future
+	cp $(FIRMWARE_DIR)/mor1kx.dtb $(TFTPD_DIR)
 endif
 else
 	cp $(FIRMWARE_FILEBASE).bin $(TFTPD_DIR)/boot.bin

diff --git a/scripts/build-linux.sh b/scripts/build-linux.sh
@@ -64,7 +64,6 @@ if [ ${CPU} = mor1kx ]; then
 	DTB=mor1kx.dtb
 	ROOTFS_MD5="c9ef89b45b0d2c34d14978a21f2863bd"
 	DTB_MD5="0271bc8f63f2d928dc9536ac31a2c6b9"
-	LINUX_BRANCH=${LINUX_BRANCH:-litex_buildenv-mor1kx}
 elif [ ${CPU} = vexriscv ]; then
 	export ARCH=riscv
 	ROOTFS=riscv32-rootfs.cpio
@@ -227,7 +226,11 @@ LLV_SRC="$TOP_DIR/third_party/linux-on-litex-vexriscv"
 
         	cat << EOF > $TARGET_LINUX_BUILD_DIR/boot.json
 {
-    "Image":        "0x00000000"
+    "mor1kx.dtb":   "0x01000000",
+    "Image":        "0x00000000",
+    "bootargs": {
+        "r1":       "0x01000000"
+    }
 }
 EOF
 	elif [ ${CPU} = vexriscv ]; then

diff --git a/third_party/litedram b/third_party/litedram
diff --git a/third_party/liteeth b/third_party/liteeth
diff --git a/third_party/litepcie b/third_party/litepcie
diff --git a/third_party/litex b/third_party/litex
diff --git a/third_party/litex-boards b/third_party/litex-boards
diff --git a/third_party/migen b/third_party/migen
+5 −1		litedram/core/controller.py
+1 −1		litedram/init.py
+1 −1		litedram/phy/__init__.py
+97 −14		litedram/phy/gensdrphy.py
+38 −0		examples/targets/stream.py
+0 −38		examples/targets/tty.py
+2 −2		examples/test/test_stream.py
+11 −13		liteeth/frontend/stream.py
+8 −4		liteeth/mac/sram.py
+3 −3		test/test_examples.py
+4 −2		litepcie/core/msi.py
+5 −13		litepcie/gen.py
+1 −1		litepcie/phy/xilinx_us_x4/pcie_us_x4_support.v
+1 −1		litepcie/phy/xilinx_usp_x4/pcie_us_x4_support.v
+48 −0		litepcie/software/kernel/main.c
+1 −0		litepcie/software/user/litepcie_util.c
+9 −4		litex/build/lattice/trellis.py
+6 −6		litex/build/xilinx/symbiflow.py
+2 −0		litex/soc/cores/i2s.py
+49 −44		litex/soc/cores/spi.py
+40 −12		litex/soc/integration/soc.py
+358 −0		litex/soc/interconnect/axi.py
+1 −1		litex/soc/interconnect/csr_bus.py
+103 −41		litex/soc/software/bios/boot.c
+21 −18		litex/soc/software/liblitesdcard/spisdcard.c
+280 −3		test/test_axi.py
+13 −4		test/test_spi.py
+1 −0		litex_boards/platforms/genesys2.py
+4 −0		litex_boards/platforms/kc705.py
+1 −2		litex_boards/platforms/trellisboard.py
+1 −0		litex_boards/platforms/ulx3s.py
+27 −12		litex_boards/targets/minispartan6.py
+37 −0		migen/build/platforms/sinara/metlino.py
+1 −1		migen/build/platforms/sinara/sayma_rtm2.py
+25 −1		migen/build/xilinx/common.py