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LongArch-liguoqi-CPU

This is my graduation project

On Building

Basic architecture diagram:

架构图

supplement some infromation:

module supplement
RAT Recover Rename Map use Arch State
ROB when inst retir reg map update in aRAT
MUL 3 cycle
DIv 16 cycle
FreeList Decode Rd infro will send Freelist Rename
(Weakup)Issue this module weak up instraction use delay weak up.
but load need relay on realy load date back.

Now In buliding file is Storebuffer and ctrl

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