Got unit tests to pass.

UoB-HPC · Sep 5, 2024 · 9004700 · 9004700
1 parent 90f4850
commit 9004700
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Showing 4 changed files with 14 additions and 11 deletions.
diff --git a/src/include/simeng/arch/aarch64/helpers/auxiliaryFunctions.hh b/src/include/simeng/arch/aarch64/helpers/auxiliaryFunctions.hh
@@ -126,7 +126,6 @@ bitfieldManipulate(T value, T dest, uint8_t rotateBy, uint8_t sourceBits,
 /** Function to check if NZCV conditions hold. */
 inline bool conditionHolds(uint8_t cond, uint8_t nzcv) {
   // Due to Capstone enum changes, need to add 1 to cond
-  cond += 1;
   bool inverse = cond & 1;
   uint8_t upper = cond >> 1;
   bool n = (nzcv >> 3) & 1;

diff --git a/src/lib/arch/aarch64/InstructionMetadata.cc b/src/lib/arch/aarch64/InstructionMetadata.cc
@@ -13,7 +13,7 @@ InstructionMetadata::InstructionMetadata(const cs_insn& insn)
       implicitSourceCount(insn.detail->regs_read_count),
       implicitDestinationCount(insn.detail->regs_write_count),
       groupCount(insn.detail->groups_count),
-      cc(insn.detail->aarch64.cc - 1),
+      cc(insn.detail->aarch64.cc),
       setsFlags(insn.detail->aarch64.update_flags),
       isAlias(insn.is_alias),
       operandCount(insn.detail->aarch64.op_count) {

diff --git a/src/lib/arch/aarch64/Instruction_decode.cc b/src/lib/arch/aarch64/Instruction_decode.cc
@@ -251,14 +251,16 @@ void Instruction::decode() {
           // SME and Predicate based operations use individual op.type
           if (op.is_vreg) {
             setInstructionType(InsnType::isVectorData);
-          } else if ((AARCH64_REG_Z31 <= op.reg && op.reg >= AARCH64_REG_Z0) ||
+            std::cerr << "\t\tIsVector" << std::endl;
+          } else if ((AARCH64_REG_Z0 <= op.reg && op.reg <= AARCH64_REG_Z31) ||
                      op.reg == AARCH64_REG_ZT0) {
-            // zT0 is an SME register, but we declare it as an SVE instruction
+            // ZT0 is an SME register, but we declare it as an SVE instruction
             // due to its 1D format.
+            std::cerr << "\t\tIsSVE" << std::endl;
             setInstructionType(InsnType::isSVEData);
-          } else if (op.reg <= AARCH64_REG_S31 && op.reg >= AARCH64_REG_Q0) {
-            setInstructionType(InsnType::isScalarData);
-          } else if (op.reg <= AARCH64_REG_H31 && op.reg >= AARCH64_REG_B0) {
+          } else if ((op.reg <= AARCH64_REG_S31 && op.reg >= AARCH64_REG_Q0) ||
+                     (op.reg <= AARCH64_REG_H31 && op.reg >= AARCH64_REG_B0)) {
+            std::cerr << "\t\tIsScalar" << std::endl;
             setInstructionType(InsnType::isScalarData);
           }
 
@@ -338,7 +340,7 @@ void Instruction::decode() {
         sourceOperandsPending_++;
       }
     } else if (op.type == AARCH64_OP_PRED) {
-      setInstructionType(InsnType::isPredicate);
+      if (i == 0) setInstructionType(InsnType::isPredicate);
       if (op.access == CS_AC_READ) {
         std::cerr << "\tPred read - ";
         sourceRegisters_[sourceRegisterCount_] = csRegToRegister(op.pred.reg);

diff --git a/test/unit/aarch64/ArchInfoTest.cc b/test/unit/aarch64/ArchInfoTest.cc
@@ -31,18 +31,20 @@ class AArch64ArchInfoTest : public ::testing::Test {
       {32, 17},
       {1, 1},
       {8, static_cast<uint16_t>(sysRegisterEnums.size())},
-      {256, 64}};
+      {256, 64},
+      {64, 1}};
 
   const std::vector<simeng::RegisterFileStructure> physRegStruct = {
       {8, 96},
       {256, 128},
       {32, 48},
       {1, 128},
       {8, static_cast<uint16_t>(sysRegisterEnums.size())},
-      {256, 128}};
+      {256, 128},
+      {64, 1}};
 
   const std::vector<uint16_t> physRegQuants = {
-      96, 128, 48, 128, static_cast<uint16_t>(sysRegisterEnums.size()), 128};
+      96, 128, 48, 128, static_cast<uint16_t>(sysRegisterEnums.size()), 128, 1};
 };
 
 // Test for the getSysRegEnums() function