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Question about workflow using cross compilation
#452
opened Jan 16, 2025 by
Scarlet1ssimo
3 tasks done
Update Dispatch Issue Unit to aid performance
performance
Performance optimisation
#445
opened Dec 16, 2024 by
FinnWilkinson
Gtest already imported with external LLVM
bug
Something isn't working
build
Issues with the buid process and its dependencies
tests
Testing and CI
#423
opened Aug 29, 2024 by
JosephMoore25
Integrate BP update with in-order core
enhancement
New feature or request
#407
opened Mar 11, 2024 by
ABenC377
Regression Test issue when building SimEng : "fcvtzu" ARM instruction
#404
opened Mar 11, 2024 by
elfmath
More registers required to rename all micro-ops than possible causes stalling
0.9.7
Part of SimEng Release 0.9.7
bug
Something isn't working
#400
opened Feb 23, 2024 by
JosephMoore25
More micro-operations than ROB size causes stalling and a mem leak
0.9.7
Part of SimEng Release 0.9.7
bug
Something isn't working
#399
opened Feb 23, 2024 by
JosephMoore25
Handle case of not enough physical registers to rename micro-operations
0.9.7
Part of SimEng Release 0.9.7
bug
Something isn't working
#384
opened Feb 5, 2024 by
JosephMoore25
[AArch64] Create helper functions for Load and Store instruction execution logic
code consistency
Cleaning up existing code to align with rest of project
enhancement
New feature or request
#378
opened Feb 2, 2024 by
FinnWilkinson
Config Docs Range and Core Type Clarifications
docs
Documentation
enhancement
New feature or request
#376
opened Jan 26, 2024 by
dANW34V3R
Zero register destination operands in multi-destination register AArch64 instructions
bug
Something isn't working
#375
opened Jan 26, 2024 by
jj16791
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