Skip to content

Commit

Permalink
[AIE2P] Update AIE2PGenInstrInfo.td
Browse files Browse the repository at this point in the history
  • Loading branch information
mludevid committed Jan 15, 2025
1 parent 1b33d5b commit 6afb6d9
Show file tree
Hide file tree
Showing 10 changed files with 3,485 additions and 2,897 deletions.
1,764 changes: 1,190 additions & 574 deletions llvm/lib/Target/AIE/Disassembler/AIE2PGenDecoderMethods.inc

Large diffs are not rendered by default.

88 changes: 44 additions & 44 deletions llvm/lib/Target/AIE/aie2p/AIE2PGenInstrInfo.td

Large diffs are not rendered by default.

88 changes: 44 additions & 44 deletions llvm/lib/Target/AIE/aie2p/AIE2PGenSchedule.td

Large diffs are not rendered by default.

201 changes: 101 additions & 100 deletions llvm/lib/Target/AIE/aie2p/AIE2PInstrInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1327,106 +1327,107 @@ AIE2PInstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*SrcOp=*/
{/*OpIdx=*/4, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
case AIE2P::VLDB_FILLX_512:
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/0, /*SubRegIdx=*/AIE2P::sub_ptr},
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_fifo},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_avail}},
/*SrcOp=*/
{/*OpIdx=*/5, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/SplitPLFRReg}}};
case AIE2P::VLDA_FILL_512:
case AIE2P::VLDB_FILL_512:
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/0, /*SubRegIdx=*/AIE2P::sub_ptr},
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_fifo},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_avail}},
/*SrcOp=*/
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/SplitPLFRReg}}};

case AIE2P::VLDB_POPX_512:
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
/*SrcOp=*/
{/*OpIdx=*/6, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/SplitPLFRReg}}};
case AIE2P::VLDA_POP_512_normal_pop:
case AIE2P::VLDA_POP_544_normal_pop:
case AIE2P::VLDA_POP_576_normal_pop:
case AIE2P::VLDA_POP_640_normal_pop:
case AIE2P::VLDA_POP_704_normal_pop:
case AIE2P::VLDB_POP_512_normal_pop:
case AIE2P::VLDB_POP_544_normal_pop:
case AIE2P::VLDB_POP_576_normal_pop:
case AIE2P::VLDB_POP_640_normal_pop:
case AIE2P::VLDB_POP_704_normal_pop:
case AIE2P::VLDA_POP_512_fifo_1d_pop:
case AIE2P::VLDA_POP_544_fifo_1d_pop:
case AIE2P::VLDA_POP_576_fifo_1d_pop:
case AIE2P::VLDA_POP_640_fifo_1d_pop:
case AIE2P::VLDA_POP_704_fifo_1d_pop:
case AIE2P::VLDB_POP_512_fifo_1d_pop:
case AIE2P::VLDB_POP_544_fifo_1d_pop:
case AIE2P::VLDB_POP_576_fifo_1d_pop:
case AIE2P::VLDB_POP_640_fifo_1d_pop:
case AIE2P::VLDB_POP_704_fifo_1d_pop:
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
/*SrcOp=*/
{/*OpIdx=*/4, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/SplitPLFRReg}}};
case AIE2P::VLDA_POP_512_2D:
case AIE2P::VLDA_POP_544_2D:
case AIE2P::VLDA_POP_576_2D:
case AIE2P::VLDA_POP_640_2D:
case AIE2P::VLDA_POP_704_2D:
case AIE2P::VLDB_POP_512_2D:
case AIE2P::VLDB_POP_544_2D:
case AIE2P::VLDB_POP_576_2D:
case AIE2P::VLDB_POP_640_2D:
case AIE2P::VLDB_POP_704_2D:
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
/*SrcOp=*/
{/*OpIdx=*/5, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/SplitPLFRReg}},
TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2P::sub_dim_count}},
/*SrcOp=*/
{/*OpIdx=*/6, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
case AIE2P::VLDA_POP_512_3D:
case AIE2P::VLDA_POP_544_3D:
case AIE2P::VLDA_POP_576_3D:
case AIE2P::VLDA_POP_640_3D:
case AIE2P::VLDA_POP_704_3D:
case AIE2P::VLDB_POP_512_3D:
case AIE2P::VLDB_POP_544_3D:
case AIE2P::VLDB_POP_576_3D:
case AIE2P::VLDB_POP_640_3D:
case AIE2P::VLDB_POP_704_3D:
return {
TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
/*SrcOp=*/
{/*OpIdx=*/6, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/SplitPLFRReg}},
TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2P::sub_dim_count},
{/*OpIdx=*/5,
/*SubRegIdx=*/AIE2P::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/
{/*OpIdx=*/7, /*SubRegIdx=*/AIE2P::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
// case AIE2P::VLDB_FILLX_512:
// return {TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/0, /*SubRegIdx=*/AIE2P::sub_ptr},
// {/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_fifo},
// {/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_avail}},
// /*SrcOp=*/
// {/*OpIdx=*/5, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/SplitPLFRReg}}};
// case AIE2P::VLDA_FILL_512:
// case AIE2P::VLDB_FILL_512:
// return {TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/0, /*SubRegIdx=*/AIE2P::sub_ptr},
// {/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_fifo},
// {/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_avail}},
// /*SrcOp=*/
// {/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/SplitPLFRReg}}};

// case AIE2P::VLDB_POPX_512:
// return {TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
// {/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
// {/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
// /*SrcOp=*/
// {/*OpIdx=*/6, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/SplitPLFRReg}}};
// case AIE2P::VLDA_POP_512_normal_pop:
// case AIE2P::VLDA_POP_544_normal_pop:
// case AIE2P::VLDA_POP_576_normal_pop:
// case AIE2P::VLDA_POP_640_normal_pop:
// case AIE2P::VLDA_POP_704_normal_pop:
// case AIE2P::VLDB_POP_512_normal_pop:
// case AIE2P::VLDB_POP_544_normal_pop:
// case AIE2P::VLDB_POP_576_normal_pop:
// case AIE2P::VLDB_POP_640_normal_pop:
// case AIE2P::VLDB_POP_704_normal_pop:
// case AIE2P::VLDA_POP_512_fifo_1d_pop:
// case AIE2P::VLDA_POP_544_fifo_1d_pop:
// case AIE2P::VLDA_POP_576_fifo_1d_pop:
// case AIE2P::VLDA_POP_640_fifo_1d_pop:
// case AIE2P::VLDA_POP_704_fifo_1d_pop:
// case AIE2P::VLDB_POP_512_fifo_1d_pop:
// case AIE2P::VLDB_POP_544_fifo_1d_pop:
// case AIE2P::VLDB_POP_576_fifo_1d_pop:
// case AIE2P::VLDB_POP_640_fifo_1d_pop:
// case AIE2P::VLDB_POP_704_fifo_1d_pop:
// return {TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
// {/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
// {/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
// /*SrcOp=*/
// {/*OpIdx=*/4, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/SplitPLFRReg}}};
// case AIE2P::VLDA_POP_512_2D:
// case AIE2P::VLDA_POP_544_2D:
// case AIE2P::VLDA_POP_576_2D:
// case AIE2P::VLDA_POP_640_2D:
// case AIE2P::VLDA_POP_704_2D:
// case AIE2P::VLDB_POP_512_2D:
// case AIE2P::VLDB_POP_544_2D:
// case AIE2P::VLDB_POP_576_2D:
// case AIE2P::VLDB_POP_640_2D:
// case AIE2P::VLDB_POP_704_2D:
// return {TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
// {/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
// {/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
// /*SrcOp=*/
// {/*OpIdx=*/5, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/SplitPLFRReg}},
// TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/4,
// /*SubRegIdx=*/AIE2P::sub_dim_count}},
// /*SrcOp=*/
// {/*OpIdx=*/6, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/Split2DReg}}};
// case AIE2P::VLDA_POP_512_3D:
// case AIE2P::VLDA_POP_544_3D:
// case AIE2P::VLDA_POP_576_3D:
// case AIE2P::VLDA_POP_640_3D:
// case AIE2P::VLDA_POP_704_3D:
// case AIE2P::VLDB_POP_512_3D:
// case AIE2P::VLDB_POP_544_3D:
// case AIE2P::VLDB_POP_576_3D:
// case AIE2P::VLDB_POP_640_3D:
// case AIE2P::VLDB_POP_704_3D:
// return {
// TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2P::sub_ptr},
// {/*OpIdx=*/2, /*SubRegIdx=*/AIE2P::sub_fifo},
// {/*OpIdx=*/3, /*SubRegIdx=*/AIE2P::sub_avail}},
// /*SrcOp=*/
// {/*OpIdx=*/6, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/SplitPLFRReg}},
// TiedRegOperands{
// /*DstOps=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2P::sub_dim_count},
// {/*OpIdx=*/5,
// /*SubRegIdx=*/AIE2P::sub_hi_dim_then_sub_dim_count}},
// /*SrcOp=*/
// {/*OpIdx=*/7, /*SubRegIdx=*/AIE2P::NoSubRegister,
// /*SubRegsSplit=*/Split3DReg}}};
default:
return {};
}
Expand Down
Loading

0 comments on commit 6afb6d9

Please sign in to comment.