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20161110_1455
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@hoglet67 hoglet67 released this 05 Oct 10:50
· 30 commits to master since this release
20161110_1455
e3c001a

6502 Co Pro now uses the 65C02 version of Arlet's 6502 core.

Arlet's 6502 core is very well regarded over on 6502.org, and is specifically designed to get the most out of registered FPGA block RAM without needing to insert a wait state. The update to the 65C02 instruction set was done a few months ago by myself and BigEd.

6502 Co Pro speeds are now 4MHz/8MHz/16MHz and 64MHz.

i.e. Co Pro 3 is now twice as fast, due to the use of Arlet's core.

6502 Co Pro has access to 1MB of external RAM using bank switching.

This is the cool new feature that we've been thinking about for a while.

The 6502 memory map is spilt into 8K pages via a set of paging eight registers at &FEE0-&FEE7:

  • the register at &FEE0 controls the mapping of 0x0000-0x1FFF
  • the register at &FEE1 controls the mapping of 0x2000-0x3FFF, etc
  • page values of 0x00-0x07 are directed to fast internal block RAM (and this is the default).
  • page values of 0x80-0xFF are directed to slower external static RAM.

To test this, there is now a variant of the Co Pro Conway Life implementation that uses this bank switched memory support much larger patterns. More on this later in the Conway Life Thread

It's now possible for someone to port Alan Cox's Fuzix to run on the 6502 Co Pro in the Beeb.

32016 Co Pro is slightly faster.

ROM accesses now have one less wait state.

Other Co Processors.

None of the other Co Processors have changed.

Compatibility.

Please let me know if you have any issue with this release. I'm aware that the last release didn't seem to work on the latest batch of boards from Jason, for reasons we have yet to fathom. There is nothing in this release that I would expect to have fixed that.

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