20171007_0719

Further improvements to reconfiguration (*FX 151,230,N) reliability, esp. ARM2

20171003_0811

Co Pro 6502: updated speeds to 3, 4, 16, 64 MHz

Co Pro 6809: Updated Client ROM to v1.05

Co Pro PDP11: Updated Client ROM to v0.27a

Be more conservative with timing within ICAP_core (might address some unreliability with *FX 151,230,N)

20170514_1320

Patch release (for Jason at ABUG Cambridge) to deal with slower SRAM

80x86 Co Pro reduced to 12MHz

ARM2 Co Pro additional wait state added

20161110_1455

6502 Co Pro now uses the 65C02 version of Arlet's 6502 core.

Arlet's 6502 core is very well regarded over on 6502.org, and is specifically designed to get the most out of registered FPGA block RAM without needing to insert a wait state. The update to the 65C02 instruction set was done a few months ago by myself and BigEd.

6502 Co Pro speeds are now 4MHz/8MHz/16MHz and 64MHz.

i.e. Co Pro 3 is now twice as fast, due to the use of Arlet's core.

6502 Co Pro has access to 1MB of external RAM using bank switching.

This is the cool new feature that we've been thinking about for a while.

The 6502 memory map is spilt into 8K pages via a set of paging eight registers at &FEE0-&FEE7:

• the register at &FEE0 controls the mapping of 0x0000-0x1FFF
• the register at &FEE1 controls the mapping of 0x2000-0x3FFF, etc
• page values of 0x00-0x07 are directed to fast internal block RAM (and this is the default).
• page values of 0x80-0xFF are directed to slower external static RAM.

To test this, there is now a variant of the Co Pro Conway Life implementation that uses this bank switched memory support much larger patterns. More on this later in the Conway Life Thread

It's now possible for someone to port Alan Cox's Fuzix to run on the 6502 Co Pro in the Beeb.

32016 Co Pro is slightly faster.

ROM accesses now have one less wait state.

Other Co Processors.

None of the other Co Processors have changed.

Compatibility.

Please let me know if you have any issue with this release. I'm aware that the last release didn't seem to work on the latest batch of boards from Jason, for reasons we have yet to fathom. There is nothing in this release that I would expect to have fixed that.

20160228_1555

Added 32016 Co Pro

Added ARM2 Co Pro

Added SPI Co Pro Bridge (for PiTubeClient) (this is merged into the Null Co Pro)

Retired original 4MHz 65C102 Co Pro with 64KB external RAM (replaced by one with internal RAM)

Renumbered designs:

  0 - 0 0 0 0 -   4MHz 65C102 ( 64KB internal RAM,   AlanD core)
  1 - 0 0 0 1 -   8MHz 65C102 ( 64KB internal RAM,   AlanD core)
  2 - 0 0 1 0 -  16MHz 65C102 ( 64KB internal RAM,   AlanD core)
  3 - 0 0 1 1 -  32MHz 65C102 ( 64KB internal RAM,   AlanD core)
  4 - 0 1 0 0 -   8MHz Z80    ( 64KB external RAM,     T80 core)
  5 - 0 1 0 1 -  32MHz Z80    ( 64KB internal RAM, NextZ80 core)
  6 - 0 1 1 0 -  56MHz Z80    ( 64KB internal RAM, NextZ80 core)
  7 - 0 1 1 1 - 112MHz Z80    ( 64KB internal RAM, NextZ80 core)
  8 - 1 0 0 0 -  16Mhz 80286  (896KB external RAM,     Zet core)  
  9 - 1 0 0 1 -   4MHz 6809   ( 64KB external RAM,   SYS09 core) 
 10 - 1 0 1 0 -  16MHz 68000  (  1MB external RAM,    TG68 core)
 11 - 1 0 1 1 -  32MHz PDP11  ( 64KB internal RAM, PDP2011 core)
 12 - 1 1 0 0 -  32MHz ARM2   (  2MB external RAM, Amber23 core)
 13 - 1 1 0 1 -  32MHz 32016  (  2MB external RAM,  m32632 core)
 14 - 1 1 1 0 -   Null / SPI  (          Raspberry Pi soft core)
 15 - 1 1 1 1 -   BIST        ( for manufacturing test purposes)

20151215_1004

This release was used by Jason in the second, third and forth batch of boards.

Only one change:
Revert "Minor tweak to ICAP_core to remove a possible configuration deadlock"

20151115_1858

Added 68000 Co Pro

6809 Co Pro: Updated Client ROM to 1.00

PDP11 Co Pro: Updated Client ROM to 0.50
PDP11 Co Pro: Implemented remapping of Page 0 between user and kernel modes
PDP11 Co Pro: Fixes to MTPI

Fixed AlanD core 65C02 bugs: D was being set in IRQ/BRK; sync was inferring a latch

Minor tweak to ICAP_core to remove a possible configuration deadlock

20150901_1358

Implemented basic reconfig from the Host using *FX 151,230,N

Extended multiboot using Xilinx GENERAL5 register to pass soft DIP state across reconfiguration boundaries

Added a Null Co Pro design in unused slots (5,6) to allow the Co Pro to be disabled

20150819_1109

Added PDP 11 Co Pro

20150328_1656

New fully synchronous tube design (using at two phase synchronizer)

Added a faster Z80 Co Pro using the NextZ80 Core

0 0 0 0 | 4MHz 65C102 (512KB external RAM using Jason's paging extensions)
0 0 0 1 | 8MHz Z80 ( 64KB external RAM)
0 0 1 0 | 4MHz 6809 ( 64KB external RAM)
0 0 1 1 | 16Mhz 80x86 (512KB external RAM)
0 1 0 0 | BIST
0 1 0 1 | unused
0 1 1 0 | unused
0 1 1 1 | unused
1 0 0 0 | 32MHz 65C102 (64KB internal RAM, boot message shows speed)
1 0 0 1 | 16MHz 65C102 (64KB internal RAM, boot message shows speed)
1 0 1 0 | 8MHz 65C102 (64KB internal RAM, boot message shows speed)
1 0 1 1 | 4MHz 65C102 (64KB internal RAM, boot message shows speed)
1 1 0 0 | 112 MHz Z80 (64KB internal RAM, now using NextZ80 core)
1 1 0 1 | 56 MHz Z80 (64KB internal RAM, now using NextZ80 core)
1 1 1 0 | 32 MHz Z80 (64KB internal RAM, now using NextZ80 core)
1 1 1 1 | 16 MHz Z80 (64KB internal RAM, now using NextZ80 core)