See Vivado™ Development Environment on amd.com |
This repository contains tutorials that augment the fundamental tutorials found in the Dynamic Function eXchange Tutorial Guide UG947. These examples show design flow features that are common to all devices that support DFX. Additional DFX tutorials can be found under device-specific categories:
Tutorial | Description |
Single Reconfigurable Partition Design using Block Design Container | This tutorial introduces the block design container feature in Vivado and how it can be leveraged to create DFX designs for Versal. |
Multiple Reconfigurable Partitions Design using Block Design Container | This tutorial demonstrates how to create design with multiple reconfigurable partitions using the block design container feature. |
Clock Region Shared by two Reconfigurable Partitions | This tutorial demonstrates a floorplan in Versal that allows sharing a clock region between two reconfigurable partitions. |
JTAG and HSDP based debugging for Versal DFX Designs | This tutorial demonstrates debug methodologies for DFX designs in Versal using JTAG and HSDP. |
Disjoint pblock solutions for remote clocking resources | This tutorial demonstrates solutions for resolving resource overlap errors and creating disjoint pblocks for including remote clocking in dynamic regions. |
Linux-based partial image delivery | This tutorial demonstrates a methodology for managing DFX via PetaLinux, taking advantage of fpgautil and libdfx to program partial images and update the device tree. |
NoC connections in DFX designs | This tutorial introduces multiple NoC connectivity options for DFX designs to transfer data between static and reconfiurable partitions. |
VNOC column sharing b/w multiple RPs | This tutorial desmonstrates how VNOC clock tiles can be shared by two reconfigurable partitions. VNOC clock tiles are automatically included in the clock routing footprint of the reconfigurable partition by the tool. |
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